1. Field of the Invention
The present invention relates generally to clock synthesizers for generating clock signals, and more particularly, to clock synthesizers which are implemented using delay locked loops having a dynamically adjustable number of delay elements located therein.
2. Related Art
A clock synthesizer generates a clock signal having a particular frequency from a reference clock, such as a crystal oscillator. As will be appreciated, it is often desirable to have the ability to generate, from a single reference clock, clock signals having frequencies which are different from the frequency of the reference clock. In other words, it is often desirable to have the ability to synthesize multiple clock frequencies from a single reference clock frequency.
FIG. 1 is a block diagram of a conventional circuit 102 which performs this function. The circuit 102 of FIG. 1 includes a phase locked loop 114 having a phase detector 106, a loop filter 108, and a voltage controlled oscillator (VCO) 110.
Phase locked loops are well known and, thus, the structure and operation of the phase locked loop 114 contained in the circuit 102 of FIG. 1 will be apparent to persons skilled in the relevant art. It is noted that phase locked loops are discussed in many publicly available documents, such as Phase Locked Loops by R.E. Best (McGraw Hill, New York, 1984).
It should also be noted that phase detectors and loop filters can be classified as voltage-based or charge-pump based. For brevity, only a charge-pump based system will be discussed here, but the following discussion is also applicable to voltage-based systems.
The circuit 102 of FIG. 1 also includes a "divide by N" divider 104 (hereafter called the "N divider") and a "divide by M" divider 112 (hereafter called the "M divider"). The N divider 104 operates to generate an output signal from an input signal, wherein the frequency of the output signal is equal to the frequency of the input signal divided by N. Similarly, the M divider 112 operates to generate an output signal from an input signal, wherein the frequency of the output signal is equal to the frequency of the input signal divided by M.
The dividers 104 and 112 can be implemented using a trigger (or T) flip flop (see FIG. 2), whose output signal S.sub.OUT changes state with each rising edge of its input signal S.sub.IN (see FIG. 3). As is apparent from the waveforms in FIG. 3, a divide by two divider (that is, where N and/or M equals 2) can be implemented using a single T flip flop. The manner in which T flip flops can be combined and used to implement dividers for other values of N and M will be apparent to persons skilled in the relevant art.
Referring again to FIG. 1, the N divider 104 and the M divider 112 operate to modify an input signal F.sub.IN (which is generated from a reference clock, not shown) and an output signal F.sub.OUT in the manner described above. These modified signals are transferred to the phase detector 106 and, consequently, these modified signals are processed by the phase locked loop 114 in a well known manner. The steady state frequency of the output signal F.sub.OUT can be described by the following relationship: EQU frequency(F.sub.OUT)=(M/N) *frequency(F.sub.IN)
Typically, F.sub.IN is a signal having a fixed frequency, and the N divider 104 and the M divider 112 are implemented such that the values of N and M can be dynamically adjusted. Thus, the frequency of F.sub.OUT can be set to a particular frequency value by appropriately setting the values of N and M. Table 1 illustrates the frequencies which can be synthesized for particular values of N and M. For example, where N is 1 and M is 3, an output signal F.sub.OUT can be generated from an input signal F.sub.IN, wherein the frequency of F.sub.OUT is three times the frequency of F.sub.IN.
TABLE 1 ______________________________________ Available Frequency Synthesizer Frequencies frequency (F.sub.OUT)/ N M frequency (F.sub.IN) ______________________________________ 1 3 3 2 3 1.5 3 3 1 1 4 4 2 4 2 3 4 1.333 1 5 5 2 5 2.5 3 5 1.667 ______________________________________
As is well known, phase locked loop circuits are plagued by many problems. These problems include jitter peaking, stability, acquisition behavior, and process variability. These and other problems of phase locked loop circuits are discussed in many publicly available documents, such as Phase Locked Loops, cited above.
As is clear from the discussion above, the conventional circuit 102 of FIG. 1 enables one to generate, from a single reference clock, clock signals having frequencies which are different from the frequency of the reference clock. However, since it utilizes a phase locked loop 114, the conventional circuit 102 suffers from the same problems that plague phase locked loop circuits.
Thus, what is required is a clock synthesizer which enables one to generate, from a single reference clock, clock signals having frequencies which are different from the frequency of the reference clock, and which does not suffer from the problems that plague phase locked loop based clock synthesizers.